Semiconductor devices of GaAs have generally been manufactured on substrates of GaAs. The typical process employs the use of vapor phase epitaxy of an active layer having a submicron thickness on a semi-insulating crystalline GaAs substrate. However, due to the frequently encountered crystallographic defects in GaAs substrates, such as lattice defects and dislocations, manufacturers continue to encounter extensions of these defects up through the active layer. These defects cause problems in obtaining uniform electrical properties in the products produced from different locations even on the same wafer. Some of the variations are such as to render the products unacceptable. In an effort to overcome these problems associated with crystal defects in the semi-insulating substrates, buffer layers have been employed between the substrate and the active layer.
Various processes have been employed to provide improved buffer layers. For example, U.S. Pat. No. 4,411,729 describes a process employed prior to the '729 invention as well as the improved process disclosed in the '729 patent. Reference may be made to this patent for details related to the manufacture of epitaxial layers. A GaAs buffer layer is described on a GaAs substrate. U.S. Pat. No. 4,511,813 discloses the use of such a buffer layer in order to obtain a low noise figure in a MESFET.
U.S. Pat. No. 4,602,965 describes the advantages and disadvantages associated with the use of buffer layers in the fabrication of FETs in GaAs. The advantages include reducing the influence of substrate defects on the active layer, while the disadvantages include complexity in the manufacturing process and elevated uncertainty as to the quality of the material in which the ion implantation occurs. Also disadvantageous is the lower resistivity of the buffer relative to the semi-insulating substrate resulting in potential isolation problems which may occur between devices on the same epitaxial layer when planar fabrication is used. Finally, it is pointed out that the substrate continues to exert some influence on the quality of the active layer.
Another application for buffer layers has the primary purpose of providing for the creation of an active layer of one material over a substrate of a different material which has a substantially different lattice constant. U.S. Pat. No. 4,551,394 provides a description of the use of a buffer layer for this application. Commencing with a silicon substrate, a germanium buffer is employed to provide a better lattice match for GaAs than is provided by silicon.
Notwithstanding the prior approaches attempted for providing a high quality transition from a substrate to an active layer where the quality of the crystalline structure is critical to good device performance to specification, there exists room for improvement. One problem associated with prior approaches was that described in U.S. Pat. No. 4,602,965. The buffer layer itself results in isolation problems. According to the present invention, an improved buffer layer structure is provided which is particularly suitable for FET manufacture according to a planar process.
It is an object of the present invention to provide GaAs based electronic devices having better and more consistent electrical performance than was previously obtainable.
It is another object of the present invention to overcome the detrimental effects on GaAs electronic devices previously caused by crystalline defects in semiconductor substrates.
It is still another object of the present invention to provide a method of manufacturing GaAs based electronic devices which manufacturing process has improved immunity to device parameter variations associated with impurities originating in the substrate.
It is yet another object of the present invention to provide these advantages in a planar process suitable for the manufacture of digital FETs.
It is also an object of the present invention to provide a defect-free active layer for the manufacture of GaAs based semiconductor products.
It is still another object of the present invention to provide a planar manufacturing process improvement making it feasible to produce both analog and digital GaAs devices on a common substrate in a single manufacturing sequence.
These and other objects of the invention are met by the invention described herein in its various implementations as well as the obvious modifications thereof which will appear to those skilled in the GaAs processing field.
A planar process which is particularly benefited by the present invention is described in commonly owned U.S. patent application Ser. No. 137,309 entitled "Self-Aligned Gate FET and Process" which was filed Dec. 23, 1987. This process results in fabrication of FETs which rely on the channel current to flow through the active layer without thinning of the active layer at the channel. This is known as a planar process due to the planar surface of the active layer on which the gate and source/drain contacts are provided. As a result, it is especially important to insure that pinch off can be accomplished reliably through the full thickness of the channel. Since the channel is the thickness of the active layer, pinch off must be through the full thickness of the active layer. If channel current is not suitably limited to the active layer, but instead is able to flow through an underlying layer, the gate voltage necessary to terminate FET conduction will be excessive and gate control over I.sub.DS will be degraded.
The composite buffer layer employed according to the invention commences with a layer of GaAs on a semi-insulating GaAs substrate. Next, a short period superlattice is formed followed by another GaAs layer. A layer of AlGaAs is then provided such that the Al content of the layer is graded. On this layer is an AlGaAs layer having an optimized Al content and no doping followed by an intrinsic GaAs layer. The intrinsic GaAs layer is the active layer which serves as the channel once it is doped for proper channel operation. The AlGaAs layer immediately beneath the GaAs channel layer provides confinement of the charge to the top GaAs layer. The mole fraction of Al in the AlGaAs layer is selected to provide optimum conduction band offset between the AlGaAs confinement layer and the channel of the FET. This structure provides substantially improved immunity to the active layer with respect to lattice defects and impurities in the substrate.